芯成半导体（上海）有限公司

行业类别：计算机、通信和其他电子设备制造业

单位简介：ISSI成立于1988年，是全球技术领先的集成电路设计企业，其分支机构分布于中国大陆、中国台湾、美国、欧洲、以色列、韩国、日本、新加坡、印度等全球各地。目前为北京君正集成电路有限公司全资子公司。ISSI专注于高性能、高品质、高可靠性的各类存储芯片（DRAM, SRAM, Flash等）的研发、设计和销售，另有子品牌LUMISSIL专注于模拟混合信号芯片的研发和销售。产品主要面向全球汽车电子、工业、医疗、网络通信及特定消费类市场。2021年度，ISSI荣获中国IC设计成就奖之十大IC设计公司，32Mb SerialRAM产品荣获中国芯优秀技术创新产品奖。 公司电话：021-50802288 公司地址：上海市浦东新区金桥镇锦绣东路2777弄25号楼

招聘专员姓名：姚静洁

投递邮箱：sara_yao@issi.com

模拟电路设计工程师（学历：本科 招聘人数：2）
【薪资】
    本科生月薪150-200/天
【工作地点】
    上海市浦东新区
【工作地区】
    上海市
【职位描述】
    Analog circuit design engineer Responsibility 1. Design/Verify/Optimize all analog circuit blocks used in memory product, including bandgap reference, amplifier, LDO, charge pump, PLL etc. 2. Guide layout designer to floorplan/implementation the layout and take responsibility of post layout simulation. 3. Design the circuit for test, mainly focus on the analog part but not limited. 4. Design high speed IO circuit with equalization tech implemented (DFE, CTLE etc), make the transmission line model and verify the signal integrity. 5. Provide support to PE for silicon test/debug Requirement 1. Good knowledge and deep understanding CMOS circuit design. 2. Familiar with EDA design tools such as spectre, hspice, finesim, Virtuoso etc. 3. Experience in high-speed IO design is preferred. 4. Experience in mix-signal circuit design, or fullchip analog circuits system plan/implement, DRAM memory design is preferred. 5. Good team player and communication skills. 6. Good learning competency, self-motivated in a flexible and dynamic environment.
投递简历
DRAM验证工程师（学历：本科 招聘人数：2）
【薪资】
    本科生月薪150-200/天
【工作地点】
    上海市浦东新区
【工作地区】
    上海市
【职位描述】
    Sara: DRAM verification engineer Responsibility: • Make the verification plan based on Spec and internal design request for completely cover function and timing verification. • Build the digital and mix-signal verification testbench to support the verification at the whole DRAM chip level. • Develop the behavior model for the fullchip and array based on the memory structure and functionality. • Verification methodology development to automate the procedure and improve the verification coverage. • Coordinate with design team to debug the design. Requirement • Knowledge and understanding of CMOS circuit design. • Familiar with EDA tools such as Spectre, finesim, NC-verilog, VCS etc. • Experience in System Verilog, UVM is a plus. • Experience in DRAM product verification is a plus. • Good team player and communication skills. • Good learning competency, self-motivated in a flexible and dynamic environment.
投递简历

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